I am a senior FPGA designer who has not been exposed for many reasons to advanced verification techniques.

My design effort has been focused on a small characterization of the external environment and a waveform-looking approach could suffice to get the work done.

Finally, I have got a chance to work on bigger and more complex designs in which the traditional and artisan approach of waveform looking is not more applicable.

So I searched the Web for “standard” approaches in the VHDL domain and I found that there are two main approaches for pure VHDL testbenches: OSVVM and UVVM.


Luca Colombini

FPGA designer with a passion for languages (both human and artificial)

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