PinnedJourney into Open Source VHDL Verification Frameworks (Part 1)I am a senior FPGA designer who has not been exposed for many reasons to advanced verification techniques.Jan 3, 2021Jan 3, 2021
PinnedJourney into Open Source VHDL Verification Frameworks(part 2)UVVM example with AXI4-Lite interfaceNov 1, 2021Nov 1, 2021
